Microchip ATtiny2313A Manual de Usario

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AVR® Instruction Set Manual
AVR® Instruction Set Manual
Introduction
This manual gives an overview and explanation of every instruction available for 8-bit AVR
® devices. Each instruction
has its own section containing functional description, it’s opcode, and syntax, the end state of the status register, and
cycle times.
The manual also contains an explanation of the different addressing modes used by AVR devices and an appendix
listing all modern AVR devices and what instruction it has available.
© 2021 Microchip Technology Inc. Manual DS40002198B-page 1
Table of Contents
Introduction.....................................................................................................................................................1
1. Instruction Set Nomenclature..................................................................................................................6
2. CPU Registers Located in the I/O Space................................................................................................8
2.1. RAMPX, RAMPY, and RAMPZ.....................................................................................................8
2.2. RAMPD........................................................................................................................................ 8
2.3. EIND.............................................................................................................................................8
3. The Program and Data Addressing Modes.............................................................................................9
3.1. Register Direct, Single Register Rd..............................................................................................9
3.2. Register Direct - Two Registers, Rd and Rr................................................................................. 9
3.3. I/O Direct.................................................................................................................................... 10
3.4. Data Direct................................................................................................................................. 10
3.5. Data Indirect............................................................................................................................... 11
3.6. Data Indirect with Pre-decrement............................................................................................... 11
3.7. Data Indirect with Post-increment.............................................................................................. 12
3.8. Data Indirect with Displacement.................................................................................................12
3.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions............. 13
3.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction................. 13
3.11. Store Program Memory Post-increment.....................................................................................14
3.12. Direct Program Addressing, JMP and CALL.............................................................................. 14
3.13. Indirect Program Addressing, IJMP and ICALL..........................................................................15
3.14. Extended Indirect Program Addressing, EIJMP and EICALL.....................................................15
3.15. Relative Program Addressing, RJMP and RCALL..................................................................... 16
4. Conditional Branch Summary............................................................................................................... 17
5. Instruction Set Summary.......................................................................................................................18
6. Instruction Description...........................................................................................................................24
6.1. ADC – Add with Carry................................................................................................................ 24
6.2. ADD – Add without Carry........................................................................................................... 25
6.3. ADIW – Add Immediate to Word................................................................................................ 26
6.4. AND – Logical AND....................................................................................................................27
6.5. ANDI – Logical AND with Immediate..........................................................................................28
6.6. ASR – Arithmetic Shift Right...................................................................................................... 29
6.7. BCLR – Bit Clear in SREG......................................................................................................... 30
6.8. BLD – Bit Load from the T Bit in SREG to a Bit in Register....................................................... 31
6.9. BRBC – Branch if Bit in SREG is Cleared..................................................................................32
6.10. BRBS – Branch if Bit in SREG is Set......................................................................................... 33
6.11. BRCC – Branch if Carry Cleared................................................................................................34
6.12. BRCS – Branch if Carry Set....................................................................................................... 35
6.13. BREAK – Break..........................................................................................................................36
6.14. BREQ – Branch if Equal.............................................................................................................36
6.15. BRGE – Branch if Greater or Equal (Signed).............................................................................37
6.16. BRHC – Branch if Half Carry Flag is Cleared.............................................................................38
AVR® Instruction Set Manual
© 2021 Microchip Technology Inc. Manual DS40002198B-page 2
6.17. BRHS – Branch if Half Carry Flag is Set....................................................................................39
6.18. BRID – Branch if Global Interrupt is Disabled............................................................................ 40
6.19. BRIE – Branch if Global Interrupt is Enabled............................................................................. 41
6.20. BRLO – Branch if Lower (Unsigned).......................................................................................... 42
6.21. BRLT – Branch if Less Than (Signed)........................................................................................43
6.22. BRMI – Branch if Minus..............................................................................................................44
6.23. BRNE – Branch if Not Equal...................................................................................................... 45
6.24. BRPL – Branch if Plus................................................................................................................46
6.25. BRSH – Branch if Same or Higher (Unsigned).......................................................................... 47
6.26. BRTC – Branch if the T Bit is Cleared........................................................................................48
6.27. BRTS – Branch if the T Bit is Set............................................................................................... 49
6.28. BRVC – Branch if Overflow Cleared.......................................................................................... 50
6.29. BRVS – Branch if Overflow Set..................................................................................................51
6.30. BSET – Bit Set in SREG............................................................................................................ 52
6.31. BST – Bit Store from Bit in Register to T Bit in SREG................................................................53
6.32. CALL – Long Call to a Subroutine..............................................................................................54
6.33. CBI – Clear Bit in I/O Register....................................................................................................55
6.34. CBR – Clear Bits in Register...................................................................................................... 56
6.35. CLC – Clear Carry Flag..............................................................................................................57
6.36. CLH – Clear Half Carry Flag...................................................................................................... 57
6.37. CLI – Clear Global Interrupt Enable Bit...................................................................................... 58
6.38. CLN – Clear Negative Flag........................................................................................................ 59
6.39. CLR – Clear Register................................................................................................................. 60
6.40. CLS – Clear Sign Flag................................................................................................................61
6.41. CLT – Clear T Bit........................................................................................................................62
6.42. CLV – Clear Overflow Flag.........................................................................................................62
6.43. CLZ – Clear Zero Flag................................................................................................................63
6.44. COM – One’s Complement........................................................................................................ 64
6.45. CP – Compare............................................................................................................................65
6.46. CPC – Compare with Carry........................................................................................................66
6.47. CPI – Compare with Immediate................................................................................................. 67
6.48. CPSE – Compare Skip if Equal..................................................................................................68
6.49. DEC – Decrement...................................................................................................................... 69
6.50. DES – Data Encryption Standard...............................................................................................71
6.51. EICALL – Extended Indirect Call to Subroutine......................................................................... 72
6.52. EIJMP – Extended Indirect Jump............................................................................................... 73
6.53. ELPM – Extended Load Program Memory.................................................................................73
6.54. EOR – Exclusive OR.................................................................................................................. 75
6.55. FMUL – Fractional Multiply Unsigned........................................................................................ 76
6.56. FMULS – Fractional Multiply Signed.......................................................................................... 77
6.57. FMULSU – Fractional Multiply Signed with Unsigned................................................................79
6.58. ICALL – Indirect Call to Subroutine............................................................................................80
6.59. IJMP – Indirect Jump..................................................................................................................81
6.60. IN - Load an I/O Location to Register.........................................................................................82
6.61. INC – Increment......................................................................................................................... 83
6.62. JMP – Jump............................................................................................................................... 84
6.63. LAC – Load and Clear................................................................................................................85
6.64. LAS – Load and Set................................................................................................................... 86
AVR® Instruction Set Manual
© 2021 Microchip Technology Inc. Manual DS40002198B-page 3

Especificaciones del producto

Marca: Microchip
Categoría: No categorizado
Modelo: ATtiny2313A

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