Microchip dsPIC33CK128MP505 Manual de Usario (131 Páginas)

HRPWM with Fine Edge

Placement

dsPIC33/PIC24 Family Reference Manual

Introduction

Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on

the device variant, this manual section may not apply to all dsPIC33 devices. Please consult the note at the

beginning of the chapter in the specific device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for download from the Microchip Worldwide

Website at: www.microchip.com.

This document describes the features and use of the High-Resolution Pulse-Width Modulated (PWM) with Fine Edge

Placement. This flexible module provides features to support many types of Motor Control (MC) and Power Control

(PC) applications, including:

• AC-to-DC Converters

• DC-to-DC Converters

• AC and DC Motor Control: Brushed DC, BLDC, PMSM, ACIM, SRM, Stepper, etc.

• Inverters

• Battery Chargers

• Digital Lighting

• Power Factor Correction (PFC)

High-Level Features

• Up to Eight Independent PWM Generators, each with Dual Outputs

• Operating modes:

– Independent Edge PWM mode

– Variable Phase PWM mode

– Independent Edge PWM mode, Dual Output

– Center-Aligned PWM mode

– Double Update Center-Aligned PWM mode

– Dual Edge Center-Aligned PWM mode

• Output modes:

– Complementary

– Independent

– Push-Pull

• Dead-Time Generator

• Dead-Time Compensation

• Leading-Edge Blanking (LEB)

• Output Override for Fault Handling

• Flexible Period/Duty Cycle Updating Options

• PWM Control Inputs (PCI) for PWM Pin Overrides and External PWM Synchronization

• Advanced Triggering Options

• Combinatorial Logic Output

• PWM Event Outputs

HRPWM with Fine Edge Placement

Table of Contents

Introduction.....................................................................................................................................................1

High-Level Features....................................................................................................................................... 1

1. Registers................................................................................................................................................. 5

2. Register Maps......................................................................................................................................... 6

2.1. Common Functions Register Map................................................................................................7

2.2. PWM Generator Register Map................................................................................................... 21

3. Architecture Overview...........................................................................................................................51

4. Operation.............................................................................................................................................. 54

4.1. PWM Clocking............................................................................................................................54

4.2. PWM Generator (PG) Features..................................................................................................59

4.3. Common Features......................................................................................................................95

4.4. Lock and Write Restrictions......................................................................................................100

5. Application Examples..........................................................................................................................105

5.1. Six-Step Commutation of Three-Phase BLDC Motor...............................................................105

5.2. Three-Phase Sinusoidal Control of PMSM/ACIM Motors.........................................................114

5.3. Simple Complementary PWM Output.......................................................................................117

5.4. Cycle-by-Cycle Current Limit Mode..........................................................................................118

5.5. External Period Reset Mode.................................................................................................... 120

6. Interrupts............................................................................................................................................. 123

7. Operation in Power-Saving Modes..................................................................................................... 124

7.1. Operation in Sleep Mode..........................................................................................................124

7.2. Operation in Idle Mode............................................................................................................. 124

8. Related Application Notes...................................................................................................................125

9. Revision History.................................................................................................................................. 126

9.1. Revision A (August 2017).........................................................................................................126

9.2. Revision B (February 2018)..................................................................................................... 126

9.3. Revision C (February 2019)..................................................................................................... 126

9.4. Revision D (December 2020)................................................................................................... 126

The Microchip Website...............................................................................................................................128

Product Change Notification Service..........................................................................................................128

Customer Support...................................................................................................................................... 128

Microchip Devices Code Protection Feature..............................................................................................128

Legal Notice............................................................................................................................................... 129

Trademarks................................................................................................................................................ 129

Quality Management System..................................................................................................................... 130

HRPWM with Fine Edge Placement

Worldwide Sales and Service.....................................................................................................................131

HRPWM with Fine Edge Placement

1. Registers

There are two categories of Special Function Registers (SFRs) used to control the operation of the PWM module:

• Common, shared by all PWM Generators

• PWM Generator-specific

An ‘x’ in the register name denotes an instance of a PWM Generator.

A ‘y’ in the register name denotes an instance of a common function.

The LOCK bit in the PCLKCON register may be set in software to block writes to certain registers and bits. See 4.2

PWM Generator (PG) Features for more information. Writes to certain data and control registers are not safe at

certain times of a PWM cycle or when the module is enabled.

HRPWM with Fine Edge Placement

Registers

2. Register Maps

Section provides a brief summary of the related common High-Resolution2.1 Common Functions Register Map

PWM with Fine Edge Placement registers. Section provides a brief summary of2.2 PWM Generator Register Map

the PWM Generator registers. The corresponding registers appear after the summaries, followed by a detailed

description of each register.

HRPWM with Fine Edge Placement

Register Maps

2.1 Common Functions Register Map

Note: The number of LOGCONy and PWMEVTy registers are device-dependent. Refer to the device data sheet for

availability.

Name Bit Pos. 7 6 5 4 3 2 1 0

PCLKCON 7:0 DIVSEL[1:0] MCLKSEL[1:0]

15:8 HRRDY HRERR LOCK

FSCL 7:0 FSCL[7:0]

15:8 FSCL[15:8]

FSMINPER 7:0 FSMINPER[7:0]

15:8 FSMINPER[15:8]

MPHASE 7:0 MPHASE[7:0]

15:8 MPHASE[15:8]

MDC 7:0 MDC[7:0]

15:8 MDC[15:8]

MPER 7:0 MPER[7:0]

15:8 MPER[15:8]

LFSR 7:0 LFSR[7:0]

15:8 LFSR[14:8]

CMBTRIGL 7:0 CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN

15:8

CMBTRIGH 7:0 CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN

15:8

LOGCONy 7:0 S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]

15:8 PWMS1y[3:0] PWMS2y[3:0]

PWMEVTy 7:0 EVTySEL[3:0] EVTyPGS[2:0]

15:8 EVTyOEN EVTyPOL EVTySTRD EVTySYNC

HRPWM with Fine Edge Placement

Register Maps

2.1.1 PWM Clock Control Register

Name: PCLKCON

Legend: C = Clearable bit

Bit 15 14 13 12 11 10 9 8

HRRDY HRERR LOCK

Access R R/C R/W

Reset 0 0 0

Bit 7 6 5 4 3 2 1 0

DIVSEL[1:0] MCLKSEL[1:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 15 – HRRDY High-Resolution Ready

Note: This bit is not present on all devices. Refer to the device-specific data sheet for availability.

Value Description

1The high-resolution circuitry is ready

0The high-resolution circuitry is not ready

Bit 14 – HRERR High-Resolution Error(1,2)

Notes:

1. This bit is not present on all devices. Refer to the device-specific data sheet for availability.

2. User software may write a ‘ ’ to this location to request a reset of the High-Resolution block when HRRDY = .0 1

Value Description

1An error has occurred; PWM signals will have limited resolution

0No error has occurred; PWM signals will have full resolution when HRRDY = 1

Bit 8 – LOCK Lock

Note: A device-specific unlock sequence must be performed before this bit can be cleared. Refer to the device data

sheet for the unlock sequence.

Value Description

1Write-protected registers and bits are locked

0Write-protected registers and bits are unlocked

Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection

Value Description

11 Divide ratio is 1:16

10 Divide ratio is 1:8

01 Divide ratio is 1:4

00 Divide ratio is 1:2

Bits 1:0 – MCLKSEL[1:0] PWM Master Clock Selection

Clock sources are device-specific. Refer to the device data sheet for selections.

Note: Do not change the MCLKSEL[1:0] bits while ON (PGxCONL[15]) = .1

HRPWM with Fine Edge Placement

Register Maps

2.1.2 Frequency Scale Register

Name: FSCL

Bit 15 14 13 12 11 10 9 8

FSCL[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSCL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – FSCL[15:0] Frequency Scale Register

The value in this register is added to the frequency scaling accumulator at each pwm_master_clk. When the

accumulated value exceeds the value of FSMINPER, a clock pulse is produced.

HRPWM with Fine Edge Placement

Register Maps

2.1.3 Frequency Scaling Minimum Period Register

Name: FSMINPER

Bit 15 14 13 12 11 10 9 8

FSMINPER[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSMINPER[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – FSMINPER[15:0] Frequency Scaling Minimum Period Register

This register holds the minimum clock period (maximum clock frequency) that can be produced by the frequency

scaling circuit.

HRPWM with Fine Edge Placement

Register Maps

2.1.4 Master Phase Register

Name: MPHASE

Bit 15 14 13 12 11 10 9 8

MPHASE[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

MPHASE[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – MPHASE[15:0] Master Phase Register

This register holds the phase offset value that can be shared by multiple PWM Generators.

HRPWM with Fine Edge Placement

Register Maps

2.1.5 Master Duty Cycle Register

Name: MDC

Bit 15 14 13 12 11 10 9 8

MDC[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

MDC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – MDC[15:0] Master Duty Cycle Register

This register holds the duty cycle value that can be shared by multiple PWM Generators.

Note: Duty cycle values less than 0x0008 should not be used (0x0020 in High-Resolution mode).

HRPWM with Fine Edge Placement

Register Maps

2.1.7 Linear Feedback Shift Register

Name: LFSR

Bit 15 14 13 12 11 10 9 8

LFSR[14:8]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

LFSR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 14:0 – LFSR[14:0] Linear Feedback Shift Register

A read of this register will provide a 15-bit pseudorandom value.

HRPWM with Fine Edge Placement

Register Maps

2.1.8 Combinational Trigger Register Low

Name: CMBTRIGL

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – CTA8EN Enable Trigger Output from PWM Generator #8 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 6 – CTA7EN Enable Trigger Output from PWM Generator #7 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 5 – CTA6EN Enable Trigger Output from PWM Generator #6 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 4 – CTA5EN Enable Trigger Output from PWM Generator #5 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 3 – CTA4EN Enable Trigger Output from PWM Generator #4 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 2 – CTA3EN Enable Trigger Output from PWM Generator #3 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 1 – CTA2EN Enable Trigger Output from PWM Generator #2 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 0 – CTA1EN Enable Trigger Output from PWM Generator #1 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

HRPWM with Fine Edge Placement

Register Maps

2.1.9 Combinational Trigger Register High

Name: CMBTRIGH

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – CTB8EN Enable Trigger Output from PWM Generator #8 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 6 – CTB7EN Enable Trigger Output from PWM Generator #7 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 5 – CTB6EN Enable Trigger Output from PWM Generator #6 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 4 – CTB5EN Enable Trigger Output from PWM Generator #5 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 3 – CTB4EN Enable Trigger Output from PWM Generator #4 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 2 – CTB3EN Enable Trigger Output from PWM Generator #3 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 1 – CTB2EN Enable Trigger Output from PWM Generator #2 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

Bit 0 – CTB1EN Enable Trigger Output from PWM Generator #1 as Source for Combinational Trigger B

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger B signal

0Disabled

HRPWM with Fine Edge Placement

Register Maps

2.1.10 Combinatorial PWM Logic Control Register y

Name: LOGCONy

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is device-

dependent. Refer to the device data sheet for availability.

Bit 15 14 13 12 11 10 9 8

PWMS1y[3:0] PWMS2y[3:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 15:12 – PWMS1y[3:0] Combinatorial PWM Logic Source #1 Selection

Note: Logic function input will be connected to ‘ ’ if the PWM channel is not present.0

Value Description

1111 PWM8L

1110 PWM8H

1101 PWM7L

1100 PWM7H

1011 PWM6L

1010 PWM6H

1001 PWM5L

1000 PWM5H

0111 PWM4L

0110 PWM4H

0101 PWM3L

0100 PWM3H

0011 PWM2L

0010 PWM2H

0001 PWM1L

0000 PWM1H

Bits 11:8 – PWMS2y[3:0] Combinatorial PWM Logic Source #2 Selection

Note: Logic function input will be connected to ‘ ’ if the PWM channel is not present.0

Value Description

1111 PWM8L

1110 PWM8H

1101 PWM7L

1100 PWM7H

1011 PWM6L

1010 PWM6H

1001 PWM5L

1000 PWM5H

0111 PWM4L

0110 PWM4H

0101 PWM3L

0100 PWM3H

0011 PWM2L

0010 PWM2H

0001 PWM1L

HRPWM with Fine Edge Placement

Register Maps

Value Description

0000 PWM1H

Bit 7 – S1yPOL Combinatorial PWM Logic Source #1 Polarity

Value Description

1Input is inverted

0Input is positive logic

Bit 6 – S2yPOL Combinatorial PWM Logic Source #2 Polarity

Value Description

1Input is inverted

0Input is positive logic

Bits 5:4 – PWMLFy[1:0] Combinatorial PWM Logic Function Selection

Value Description

11 Reserved

10 PWMS1y ^ PWMS2y (XOR)

01 PWMS1y & PWMS2y (AND)

00 PWMS1y | PWMS2y (OR)

Bits 2:0 – PWMLFyD[2:0] Combinatorial PWM Logic Destination Selection

Note: Instances of y = A, C, E of LOGCONy assign logic function output to the PWMxH pin. Instances of y = B, D, F

of LOGCONy assign logic function to the PWMxL pin.

Value Description

111 Logic function is assigned to PWM8

110 Logic function is assigned to PWM7

101 Logic function is assigned to PWM6

100 Logic function is assigned to PWM5

011 Logic function is assigned to PWM4

010 Logic function is assigned to PWM3

001 Logic function is assigned to PWM2

000 No assignment, combinatorial PWM logic function is disabled

HRPWM with Fine Edge Placement

Register Maps

2.1.11 PWM Event Output Control Register y

Name: PWMEVTy

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is

device-dependent. Refer to the device data sheet for availability.

Bit 15 14 13 12 11 10 9 8

EVTyOEN EVTyPOL EVTySTRD EVTySYNC

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

EVTySEL[3:0] EVTyPGS[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 15 – EVTyOEN PWM Event Output Enable

Value Description

1Event output signal is output on the PWMEy pin

0Event output signal is internal only

Bit 14 – EVTyPOL PWM Event Output Polarity

Value Description

1Event output signal is active-low

0Event output signal is active-high

Bit 13 – EVTySTRD PWM Event Output Stretch Disable

Note: The event signal is stretched using peripheral_clk because different PWM Generators may be operating from

different clock sources.

Value Description

1Event output signal pulse width is not stretched

0Event output signal is stretched to eight PWM clock cycles minimum

Bit 12 – EVTySYNC PWM Event Output Sync

Event output signal pulse will be synchronized to peripheral_clk.

Value Description

1Event output signal is synchronized to the system clock

0Event output is not synchronized to the system clock

Bits 7:4 – EVTySEL[3:0] PWM Event Selection

Note: This is the PWM Generator output signal prior to Output mode logic and any output override logic.

Value Description

1111 High-resolution error event signal

1110-1010 Reserved

1001 ADC Trigger 2 signal

1000 ADC Trigger 1 signal

0111 STEER signal (available in Push-Pull Output modes only)

0110 CAHALF signal (available in Center-Aligned modes only)

0101 PCI Fault active output signal

0100 PCI current limit active output signal

0011 PCI feed-forward active output signal

0010 PCI Sync active output signal

0001 PWM Generator output signal

(1)

0000 Source is selected by the [2:0] bitsPGTRGSEL

HRPWM with Fine Edge Placement

Register Maps

Bits 2:0 – EVTyPGS[2:0] PWM Event Source Selection

Note: No event will be produced if the selected PWM Generator is not present.

Value Description

111 PWM Generator #8

110 PWM Generator #7

101 PWM Generator #6

100 PWM Generator #5

011 PWM Generator #4

010 PWM Generator #3

001 PWM Generator #2

000 PWM Generator #1

HRPWM with Fine Edge Placement

Register Maps

2.2 PWM Generator Register Map

Legend: x = PWM Generator #; y = F, CL, FF or S.

Name Bit Pos. 7 6 5 4 3 2 1 0

Reserved

PGxCONL 7:0 HREN CLKSEL[1:0] MODSEL[2:0]

15:8 ON TRGCNT[2:0]

PGxCONH 7:0 Reserved TRGMOD SOCS[3:0]

15:8 MDCSEL MPERSEL MPHSEL MSTEN UPDMOD[2:0]

PGxSTAT 7:0 TRSET TRCLR CAP UPDATE UPDREQ STEER CAHALF TRIG

15:8 SEVT FLTEVT CLEVT FFEVT SACT FLTACT CLACT FFACT

PGxIOCONL 7:0 FLTDAT[1:0] CLDAT[1:0] FFDAT[1:0] DBDAT[1:0]

15:8 CLMOD SWAP OVRENH OVRENL OVRDAT[1:0] OSYNC[1:0]

PGxIOCONH 7:0 PMOD[1:0] PENH PENL POLH POLL

15:8 CAPSRC[2:0] DTCMPSEL

PGxEVTL 7:0 UPDTRG[1:0] PGTRGSEL[2:0]

15:8 ADTR1PS[4:0] ADTR1EN3 ADTR1EN2 ADTR1EN1

PGxEVTH 7:0 ADTR2EN3 ADTR2EN2 ADTR2EN1 ADTR1OFS[4:0]

15:8 FLTIEN CLIEN FFIEN SIEN IEVTSEL[1:0]

PGxyPCIL 7:0 SWTERM PSYNC PPS PSS[4:0]

15:8 TSYNCDIS TERM[2:0] AQPS AQSS[2:0]

PGxyPCIH 7:0 SWPCI SWPCIM[1:0] LATMOD TQPS TQSS[2:0]

15:8 BPEN BPSEL[2:0] ACP[2:0]

Reserved

PGxLEBL 7:0 LEB[10:6] [2:0]

15:8 LEB[18:11]

PGxLEBH 7:0 PHR PHF PLR PLF

15:8 PWMPCI[2:0]

PGxPHASE 7:0 PGxPHASE[7:0]

15:8 PGxPHASE[15:8]

Reserved

PGxDC 7:0 PGxDC[7:0]

15:8 PGxDC[15:8]

PGxDCA 7:0 PGxDCA[7:0]

15:8

PGxPER 7:0 PGxPER[7:0]

15:8 PGxPER[15:8]

PGxTRIGA 7:0 PGxTRIGA[7:0]

15:8 PGxTRIGA[15:8]

PGxTRIGB 7:0 PGxTRIGB[7:0]

15:8 PGxTRIGB[15:8]

PGxTRIGC 7:0 PGxTRIGC[7:0]

15:8 PGxTRIGC[15:8]

PGxDTL 7:0 DTL[7:0]

15:8 DTL[13:8]

PGxDTH 7:0 DTH[7:0]

15:8 DTH[13:8]

PGxCAP 7:0 PGxCAP[6:0]

15:8 PGxCAP[14:7]

HRPWM with Fine Edge Placement

Register Maps

2.2.1 PWM Generator x Control Register Low

Name: PGxCONL

Bit 15 14 13 12 11 10 9 8

ON TRGCNT[2:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

HREN CLKSEL[1:0] MODSEL[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 – ON PWM Generator x Enable

Value Description

1PWM Generator is enabled

0PWM Generator is not enabled

Bits 10:8 – TRGCNT[2:0] PWM Generator x Trigger Count Select

Value Description

111 PWM Generator produces 8 PWM cycles after triggered

110 PWM Generator produces 7 PWM cycles after triggered

101 PWM Generator produces 6 PWM cycles after triggered

100 PWM Generator produces 5 PWM cycles after triggered

011 PWM Generator produces 4 PWM cycles after triggered

010 PWM Generator produces 3 PWM cycles after triggered

001 PWM Generator produces 2 PWM cycles after triggered

000 PWM Generator produces 1 PWM cycle after triggered

Bit 7 – HREN PWM Generator x High-Resolution Enable

Note: This bit is not present on all devices. Refer to the device-specific data sheet for availability. When High-

Resolution mode is not available, this bit will read as ‘ ’.0

Value Description

1PWM Generator x operates in High-Resolution mode

0PWM Generator x operates in Standard Resolution mode

Bits 4:3 – CLKSEL[1:0] Clock Selection(1)

Notes:

1. Do not change the CLKSEL[1:0] bits while ON (PGxCONL[15]) = .1

2. The PWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty

cycle and period of the PWM Generator output.

3. This clock source should not be used when HREN (PGxCONL[7]) = .1

Value Description

11 PWM Generator uses the master clock scaled by the frequency scaling circuit

(2,3)

10 PWM Generator uses the master clock divided by the clock divider circuit

(2)

01 PWM Generator uses the master clock selected by the MCLKSEL[1:0] (PCLKCON[1:0]) control bits

00 No clock selected, PWM Generator is in the lowest power state (default)

Bits 2:0 – MODSEL[2:0] PWM Generator x Mode Selection

Value Description

111 Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle)

110 Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle)

101 Double Update Center-Aligned PWM mode

HRPWM with Fine Edge Placement

Register Maps

Value Description

100 Center-Aligned PWM mode

011 Reserved

010 Independent Edge PWM mode, dual output

001 Variable Phase PWM mode

000 Independent Edge PWM mode

HRPWM with Fine Edge Placement

Register Maps

2.2.2 PWM Generator x Control Register High

Name: PGxCONH

Bit 15 14 13 12 11 10 9 8

MDCSEL MPERSEL MPHSEL MSTEN UPDMOD[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

Reserved TRGMOD SOCS[3:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 – MDCSEL Master Duty Cycle Register Select

Value Description

1PWM Generator uses MDC register

0PWM Generator uses PGxDC register

Bit 14 – MPERSEL Master Period Register Select

Value Description

1PWM Generator uses MPER register

0PWM Generator uses PGxPER register

Bit 13 – MPHSEL Master Phase Register Select

Value Description

1PWM Generator uses MPHASE register

0PWM Generator uses PGxPHASE register

Bit 11 – MSTEN Master Update Enable

Value Description

1PWM Generator broadcasts software set of UPDREQ control bit and EOC signal to other PWM

Generators

0PWM Generator does not broadcast UPDREQ status bit state or EOC signal

Bits 10:8 – UPDMOD[2:0] PWM Buffer Update Mode Selection

See Table 4-5 for details.

Bit 7 – Reserved Maintain as ‘ ’0

Bit 6 – TRGMOD PWM Generator x Trigger Mode Selection

Value Description

1PWM Generator operates in Retriggerable mode

0PWM Generator operates in Single Trigger mode

Bits 3:0 – SOCS[3:0] Start-of-Cycle Selection bits(1,2,3)

Notes:

1. The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0]

bits if the PCI Sync function is enabled.

2. The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM

Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be

synchronized to the PWM Generator clock domain.

3. PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within

a group of four may be used to trigger another generator within the same group.

HRPWM with Fine Edge Placement

Register Maps

Value Description

1111 TRIG bit or PCI Sync function only (no hardware trigger source is selected)

1110 - 0101 Reserved

0100 Trigger output selected by PG4 or PG8 [2:0] bits (PGxEVTL[2:0])PGTRGSEL

0011 Trigger output selected by PG3 or PG7 [2:0] bits (PGxEVTL[2:0])PGTRGSEL

0010 Trigger output selected by PG2 or PG6 [2:0] bits (PGxEVTL[2:0])PGTRGSEL

0001 Trigger output selected by PG1 or PG5 [2:0] bits (PGxEVTL[2:0])PGTRGSEL

0000 Local EOC – PWM Generator is self-triggered

HRPWM with Fine Edge Placement

Register Maps

2.2.3 PWM Generator x Status Register

Name: PGxSTAT

Legend: C = Clearable bit; HS = Hardware Settable bit

Bit 15 14 13 12 11 10 9 8

SEVT FLTEVT CLEVT FFEVT SACT FLTACT CLACT FFACT

Access HS/C HS/C HS/C HS/C R R R R

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TRSET TRCLR CAP UPDATE UPDREQ STEER CAHALF TRIG

Access W W R/HS R W R R R

Reset 0 0 0 0 0 0 0 0

Bit 15 – SEVT PCI Sync Event

Value Description

1A PCI Sync event has occurred (rising edge on PCI Sync output or PCI Sync output is high when

module is enabled)

0No PCI Sync event has occurred

Bit 14 – FLTEVT PCI Fault Active Status

Value Description

1A Fault event has occurred (rising edge on PCI Fault output or PCI Fault output is high when module is

enabled)

0No Fault event has occurred

Bit 13 – CLEVT PCI Current Limit Status

Value Description

1A PCI current limit event has occurred (rising edge on PCI current limit output or PCI current limit

output is high when module is enabled)

0No PCI current limit event has occurred

Bit 12 – FFEVT PCI Feed-Forward Active Status

Value Description

1A PCI feed-forward event has occurred (the rising edge on the PCI feed-forward output or PCI feed-

forward output is high when module is enabled)

0No PCI feed-forward event has occurred

Bit 11 – SACT PCI Sync Status

Value Description

1PCI Sync output is active

0PCI Sync output is inactive

Bit 10 – FLTACT PCI Fault Active Status

Value Description

1PCI Fault output is active

0PCI Fault output is inactive

Bit 9 – CLACT PCI Current Limit Status

Value Description

1PCI current limit output is active

0PCI current limit output is inactive

Bit 8 – FFACT PCI Feed-Forward Active Status

HRPWM with Fine Edge Placement

Register Maps

Value Description

1PCI feed-forward output is active

0PCI feed-forward output is inactive

Bit 7 – TRSET PWM Generator Software Trigger Set

User software writes a ‘ ’ to this bit location to trigger a PWM Generator cycle. The bit location always reads as ‘ ’.1 0

The TRIG bit will indicate ‘ ’ when the PWM Generator is triggered.1

Bit 6 – TRCLR PWM Generator Software Trigger Clear

User software writes a ‘ ’ to this bit location to stop a PWM Generator cycle. The bit location always reads as ‘ ’. The1 0

TRIG bit will indicate ‘ ’ when the PWM Generator is not triggered.0

Bit 5 – CAP Capture Status

Value Description

1PWM Generator time base value has been captured in PGxCAP

0No capture has occurred

Bit 4 – UPDATE PWM Data Register Update Status/Control

Value Description

1PWM Data register update is pending – user Data registers are not writable

0No PWM Data register update is pending

Bit 3 – UPDREQ PWM Data Register Update Request

User software writes a ‘ ’ to this bit location to request a PWM Data register update. The bit location always reads as1

‘ ’. The UPDATE status bit will indicate a ‘ ’ when an update is pending.0 1

Bit 2 – STEER Output Steering Status (Push-Pull Output mode only)

Value Description

1PWM Generator is in 2nd cycle of Push-Pull mode

0PWM Generator is in 1st cycle of Push-Pull mode

Bit 1 – CAHALF Half Cycle Status (Center-Aligned modes only)

Value Description

1PWM Generator is in 2nd half of time base cycle

0PWM Generator is in 1st half of time base cycle

Bit 0 – TRIG Trigger Status

Value Description

1PWM Generator is triggered and PWM cycle is in progress

0No PWM cycle is in progress

HRPWM with Fine Edge Placement

Register Maps

2.2.4 PWM Generator x I/O Control Register Low

Name: PGxIOCONL

Bit 15 14 13 12 11 10 9 8

CLMOD SWAP OVRENH OVRENL OVRDAT[1:0] OSYNC[1:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FLTDAT[1:0] CLDAT[1:0] FFDAT[1:0] DBDAT[1:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 – CLMOD Current Limit Mode Select

Value Description

1If PCI current limit is active, then the PWMxH and PWMxL output signals are inverted (bit flipping), and

the CLDAT[1:0] bits are not used

0If PCI current limit is active, then the CLDAT[1:0] bits define the PWM output levels

Bit 14 – SWAP Swap PWM Signals to PWMxH and PWMxL Device Pins

Value Description

1The PWMxH signal is connected to the PWMxL pin and the PWMxL signal is connected to the PWMxH

0PWMxH/L signals are mapped to their respective pins

Bit 13 – OVRENH User Override Enable for PWMxH Pin

Value Description

1OVRDAT[1] provides data for output on the PWMxH pin

0PWM Generator provides data for the PWMxH pin

Bit 12 – OVRENL User Override Enable for PWMxL Pin

Value Description

1OVRDAT[0] provides data for output on the PWMxL pin

0PWM Generator provides data for the PWMxL pin

Bits 11:10 – OVRDAT[1:0] Data for PWMxH/PWMxL Pins if Override is Enabled

Description

If OVRENH = , then OVRDAT[1] provides data for PWMxH.1

If OVRENL = , then OVRDAT[0] provides data for PWMxL.1

Bits 9:8 – OSYNC[1:0] User Output Override Synchronization Control

Value Description

11 Reserved

10 User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur when specified by the

UPDMOD[2:0] bits in the PGxCONH register

01 User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur immediately (as soon as

possible)

00 User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits are synchronized to the local

PWM time base (next start of cycle)

Bits 7:6 – FLTDAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active

Description

If Fault is active, then FLTDAT[1] provides data for PWMxH.

If Fault is active, then FLTDAT[0] provides data for PWMxL.

HRPWM with Fine Edge Placement

Register Maps

Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if CLMT Event is Active

Description

If current limit is active, then CLDAT[1] provides data for PWMxH.

If current limit is active, then CLDAT[0] provides data for PWMxL.

Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active

Description

If feed-forward is active, then FFDAT[1] provides data for PWMxH.

If feed-forward is active, then FFDAT[0] provides data for PWMxL.

Bits 1:0 – DBDAT[1:0] Data for PWMxH/PWMxL Pins if Debug Mode is Active

Description

If Debug mode is active and PTFRZ = , then DBDAT[1] provides data for PWMxH.1

If Debug mode is active and PTFRZ = , then DBDAT[0] provides data for PWMxL.1

HRPWM with Fine Edge Placement

Register Maps

2.2.6 PWM Generator x Event Register Low

Name: PGxEVTL

Bit 15 14 13 12 11 10 9 8

ADTR1PS[4:0] ADTR1EN3 ADTR1EN2 ADTR1EN1

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

UPDTRG[1:0] PGTRGSEL[2:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection

Value Description

11111 1:32

. . . . . .

00010 1:3

00001 1:2

00000 1:1

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable

Value Description

1PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 1

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable

Value Description

1PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 1

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable

Value Description

1PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 1

Bits 4:3 – UPDTRG[1:0] Update Trigger Select

Value Description

11 A write of the PGxTRIGA register automatically sets the UPDREQ bit

10 A write of the PGxPHASE register automatically sets the UPDREQ bit

01 A write of the PGxDC register automatically sets the UPDREQ bit

00 User must set the bit (PGxSTAT[3]) manuallyUPDREQ

Bits 2:0 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection

Note: These events are derived from the internal PWM Generator time base comparison events.

Value Description

111 Reserved

110 Reserved

101 Reserved

100 Reserved

011 PGxTRIGC compare event is the PWM Generator trigger

010 PGxTRIGB compare event is the PWM Generator trigger

001 PGxTRIGA compare event is the PWM Generator trigger

000 EOC event is the PWM Generator trigger

HRPWM with Fine Edge Placement

Register Maps

2.2.7 PWM Generator x Event Register High

Name: PGxEVTH

Bit 15 14 13 12 11 10 9 8

FLTIEN CLIEN FFIEN SIEN IEVTSEL[1:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADTR2EN3 ADTR2EN2 ADTR2EN1 ADTR1OFS[4:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 – FLTIEN PCI Fault Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Fault active signal.

Value Description

1Fault interrupt is enabled

0Fault interrupt is disabled

Bit 14 – CLIEN PCI Current Limit Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI current limit active signal.

Value Description

1Current limit interrupt is enabled

0Current limit interrupt is disabled

Bit 13 – FFIEN PCI Feed-Forward Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI feed-forward active signal.

Value Description

1Feed-forward interrupt is enabled

0Feed-forward interrupt is disabled

Bit 12 – SIEN PCI Sync Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Sync active signal.

Value Description

1Sync interrupt is enabled

0Sync interrupt is disabled

Bits 9:8 – IEVTSEL[1:0] Interrupt Event Selection

Value Description

11 Time base interrupts are disabled (Sync, Fault, current limit and feed-forward events can be

independently enabled)

10 Interrupts CPU at ADC Trigger 1 event

01 Interrupts CPU at TRIGA compare event

00 Interrupts CPU at EOC

Bit 7 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable

Value Description

1PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 2

0PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 2

Bit 6 – ADTR2EN2 ADC Trigger 2 Source is PGxTRIGB Compare Event Enable

Value Description

1PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 2

HRPWM with Fine Edge Placement

Register Maps

Value Description

0PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 2

Bit 5 – ADTR2EN1 ADC Trigger 2 Source is PGxTRIGA Compare Event Enable

Value Description

1PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 2

0PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 2

Bits 4:0 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection

Value Description

11111 Offset by 31 trigger events

. . . . . .

00010 Offset by 2 trigger events

00001 Offset by 1 trigger event

00000 No offset

HRPWM with Fine Edge Placement

Register Maps

2.2.8 PWM Generator xy PCI Register Low (x = PWM Generator #; y = F, CL, FF or S)

Name: PGxyPCIL

Bit 15 14 13 12 11 10 9 8

TSYNCDIS TERM[2:0] AQPS AQSS[2:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

SWTERM PSYNC PPS PSS[4:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 – TSYNCDIS Termination Synchronization Disable

Value Description

1Termination of latched PCI occurs immediately

0Termination of latched PCI occurs at PWM EOC

Bits 14:12 – TERM[2:0] Termination Event Selection

Notes:

1. PCI sources are device-dependent; refer to the device data sheet for availability.

2. Do not use this selection when the ACP[2:0] bits (PGxyPCIH[10:8]) are set for latched on any edge.

Value Description

111 Selects PCI Source #9(1)

110 Selects PCI Source #8(1)

101 Selects PCI Source #1 (PWM Generator output selected by the [2:0] bits)PWMPCI

100 PGxTRIGC trigger event

011 PGxTRIGB trigger event

010 PGxTRIGA trigger event

001 Auto-Terminate: Terminate when PCI source transitions from active to inactive

(2)

000 Manual Terminate: Terminate on a write of ‘ ’ to the SWTERM bit location1

Bit 11 – AQPS Acceptance Qualifier Polarity Select

Value Description

1Inverted

0Not inverted

Bits 10:8 – AQSS[2:0] Acceptance Qualifier Source Selection

Value Description

111 SWPCI control bit only (qualifier forced to ‘ ’)0

110 Selects PCI Source #9

101 Selects PCI Source #8

100 Selects PCI Source #1 (PWM Generator output selected by the [2:0] bits)PWMPCI

011 PWM Generator is triggered

010 LEB is active

001 Duty cycle is active (base PWM Generator signal)

000 No acceptance qualifier is used (qualifier forced to ‘ ’)1

Bit 7 – SWTERM PCI Software Termination

A write of ‘ ’ to this location will produce a termination event. This bit location always reads as ‘ ’.1 0

Bit 6 – PSYNC PCI Synchronization Control

HRPWM with Fine Edge Placement

Register Maps

2.2.9 PWM Generator xy PCI Register High (x = PWM Generator #; y = F, CL, FF or S)

Name: PGxyPCIH

Bit 15 14 13 12 11 10 9 8

BPEN BPSEL[2:0] ACP[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

SWPCI SWPCIM[1:0] LATMOD TQPS TQSS[2:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 – BPEN PCI Bypass Enable

Value Description

1PCI function is enabled and local PCI logic is bypassed; PWM Generator will be controlled by PCI

function in the PWM Generator selected by the [2:0] bitsBPSEL

0PCI function is not bypassed

Bits 14:12 – BPSEL[2:0] PCI Bypass Source Selection

Note: Selects ‘ ’ if the selected PWM Generator is not present.0

Value Description

111 PCI control is sourced from PWM Generator 8 PCI logic when BPEN = 1

110 PCI control is sourced from PWM Generator 7 PCI logic when BPEN = 1

101 PCI control is sourced from PWM Generator 6 PCI logic when BPEN = 1

100 PCI control is sourced from PWM Generator 5 PCI logic when BPEN = 1

011 PCI control is sourced from PWM Generator 4 PCI logic when BPEN = 1

010 PCI control is sourced from PWM Generator 3 PCI logic when BPEN = 1

001 PCI control is sourced from PWM Generator 2 PCI logic when BPEN = 1

000 PCI control is sourced from PWM Generator 1 PCI logic when BPEN = 1

Bits 10:8 – ACP[2:0] PCI Acceptance Criteria Selection

Note:

1. Don’t use this selection when the TERM[2:0] bits (PGxyPCIL[14:12]) are set to auto-termination.

Value Description

111 Reserved

110 Reserved

101 Latched any edge(1)

100 Latched rising edge

011 Latched

010 Any edge

001 Rising edge

000 Level-sensitive

Bit 7 – SWPCI Software PCI Control

Value Description

1Drives a ‘ ’ to PCI logic assigned to by the SWPCIM[1:0] control bits1

0Drives a ‘ ’ to PCI logic assigned to by the SWPCIM[1:0] control bits0

Bits 6:5 – SWPCIM[1:0] Software PCI Control Mode

Value Description

11 Reserved

10 SWPCI bit is assigned to termination qualifier logic

HRPWM with Fine Edge Placement

Register Maps

Value Description

01 SWPCI bit is assigned to acceptance qualifier logic

00 SWPCI bit is assigned to PCI acceptance logic

Bit 4 – LATMOD PCI SR Latch Mode

Value Description

1SR latch is Reset-dominant in Latched Acceptance modes

0SR latch is set-dominant in Latched Acceptance modes

Bit 3 – TQPS Termination Qualifier Polarity Select

Value Description

1Inverted

0Not inverted

Bits 2:0 – TQSS[2:0] Termination Qualifier Source Selection

Note:

1. Polarity control bit, TQPS, has no effect on these selections.

Value Description

111 SWPCI control bit only (qualifier forced to ‘ ’)1 (1)

110 Selects PCI Source #9

101 Selects PCI Source #8

100 Selects PCI Source #1 (PWM Generator output selected by the [2:0] bits)PWMPCI

011 PWM Generator is triggered

010 LEB is active

001 Duty cycle is active (base PWM Generator signal)

000 No termination qualifier used (qualifier forced to ‘ ’)1 (1)

HRPWM with Fine Edge Placement

Register Maps

2.2.10 PWM Generator x Leading-Edge Blanking Register Low

Name: PGxLEBL

Bit 15 14 13 12 11 10 9 8

LEB[18:11]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

LEB[10:6] [2:0]

Access R/W R/W R/W R/W R/W R R R

Reset 0 0 0 0 0 0 0 0

Bits 15:3 – LEB[15:3] Leading-Edge Blanking Period

Leading-Edge Blanking period. The three LSbs of the blanking time are not used, providing a blanking resolution of

eight PGx_clks. The minimum blanking period is eight PGx_clks, which occurs when LEB[15:3] = .0

Bits 2:0 – [2:0] Read-Only

HRPWM with Fine Edge Placement

Register Maps

2.2.11 PWM Generator x Leading-Edge Blanking Register High

Name: PGxLEBH

Bit 15 14 13 12 11 10 9 8

PWMPCI[2:0]

Access R/W R/W R/W

Reset 0 0 0

Bit 7 6 5 4 3 2 1 0

PHR PHF PLR PLF

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bits 10:8 – PWMPCI[2:0] PWM Source for PCI Selection

Note: The selected PWM Generator source does not affect the LEB counter. This source can be optionally used as

a PCI input, PCI qualifier, PCI terminator or PCI terminator qualifier (see the description in the PGxyPCIL and

PGxyPCIH registers for more information).

Value Description

111 PWM Generator #8 output is made available to PCI logic

110 PWM Generator #7 output is made available to PCI logic

101 PWM Generator #6 output is made available to PCI logic

100 PWM Generator #5 output is made available to PCI logic

011 PWM Generator #4 output is made available to PCI logic

010 PWM Generator #3 output is made available to PCI logic

001 PWM Generator #2 output is made available to PCI logic

000 PWM Generator #1 output is made available to PCI logic

Bit 3 – PHR PWMxH Rising Edge Trigger Enable

Value Description

1Rising edge of PWMxH will trigger the LEB duration counter

0LEB ignores the rising edge of PWMxH

Bit 2 – PHF PWMxH Falling Edge Trigger Enable

Value Description

1Falling edge of PWMxH will trigger the LEB duration counter

0LEB ignores the falling edge of PWMxH

Bit 1 – PLR PWMxL Rising Edge Trigger Enable

Value Description

1Rising edge of PWMxL will trigger the LEB duration counter

0LEB ignores the rising edge of PWMxL

Bit 0 – PLF PWMxL Falling Edge Trigger Enable

Value Description

1Falling edge of PWMxL will trigger the LEB duration counter

0LEB ignores the falling edge of PWMxL

HRPWM with Fine Edge Placement

Register Maps

2.2.12 PWM Generator x Phase Register

Name: PGxPHASE

Bit 15 14 13 12 11 10 9 8

PGxPHASE[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxPHASE[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – PGxPHASE[15:0] PWM Generator x Phase Register

HRPWM with Fine Edge Placement

Register Maps

2.2.14 PWM Generator x Duty Cycle Adjustment Register

Name: PGxDCA

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

PGxDCA[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PGxDCA[7:0] PWM Generator x Duty Cycle Adjustment Value

Depending on the state of the selected PCI source, the PGxDCA value will be added to the value in the PGxDC

register to create the effective duty cycle. When the PCI source is active, PGxDCA is added. In High-Resolution

mode, bits[2:0] are forced to ‘ ’.0

HRPWM with Fine Edge Placement

Register Maps

2.2.15 PWM Generator x Period Register

Name: PGxPER

Bit 15 14 13 12 11 10 9 8

PGxPER[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxPER[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – PGxPER[15:0] PWM Generator x Period Register

Note: Period values less than 0x0010 should not be used (0x0080 in High-Resolution mode).

HRPWM with Fine Edge Placement

Register Maps

2.2.16 PWM Generator x Trigger A Register

Name: PGxTRIGA

Bit 15 14 13 12 11 10 9 8

PGxTRIGA[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxTRIGA[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – PGxTRIGA[15:0] PWM Generator x Trigger A Register

In High-Resolution mode, bits[2:0] are forced to ‘ ’.0

HRPWM with Fine Edge Placement

Register Maps

2.2.17 PWM Generator x Trigger B Register

Name: PGxTRIGB

Bit 15 14 13 12 11 10 9 8

PGxTRIGB[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxTRIGB[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – PGxTRIGB[15:0] PWM Generator x Trigger B Register

In High-Resolution mode, bits[2:0] are forced to ‘ ’.0

HRPWM with Fine Edge Placement

Register Maps

2.2.18 PWM Generator x Trigger C Register

Name: PGxTRIGC

Bit 15 14 13 12 11 10 9 8

PGxTRIGC[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxTRIGC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – PGxTRIGC[15:0] PWM Generator x Trigger C Register

In High-Resolution mode, bits[2:0] are forced to ‘ ’.0

HRPWM with Fine Edge Placement

Register Maps

2.2.20 PWM Generator x Dead-Time Register High

Name: PGxDTH

Bit 15 14 13 12 11 10 9 8

DTH[13:8]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

DTH[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 13:0 – DTH[13:0] PWMxH Dead-Time Delay

Note: The DTH[13:11] bits are not available when HREN (PGxCONL[7]) = .0

HRPWM with Fine Edge Placement

Register Maps

2.2.21 PWM Generator x Capture Register

Name: PGxCAP

Bit 15 14 13 12 11 10 9 8

PGxCAP[14:7]

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

PGxCAP[6:0]

Access R R R R R R R R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:1 – PGxCAP[14:0] PGx Time Base Capture

PGx Time Base Capture bits.

Note: A capture event can be manually initiated in software by writing a ‘ ’ to PGxCAP[0].1

The CAP bit (PGxSTAT[5]) will indicate when a new capture value is available. A read of PGxCAP will automatically

clear the CAP bit and allow a new capture event to occur. PGxCAP[1:0] will always read as ‘ ’. In High-Resolution0

mode, PGxCAP[4:0] will always read as ‘ ’.0

Bit 0 – Read/Write

HRPWM with Fine Edge Placement

Register Maps

3. Architecture Overview

The PWM module consists of a common set of controls and features, and multiple instantiations of PWM Generators

(PGx). Each PWM Generator can be independently configured or multiple PWM Generators can be used to achieve

complex multiphase systems. PWM Generators can also be used to implement sophisticated triggering, protection

and logic functions. A high-level block diagram is shown in .Figure 3-1

Figure 3-1. PWM High-Level Block Diagram

PG1

PG2

PG8

PWM1H

PWM1L

PWM2H

PWM2L

PWM8H

PWM8L

Clock

Control

Master Data

Registers

Combinatorial

Logic

Outputs

Combinatorial

Triggers

Linear

Feedback PWM Event

Outputs

Shift Register

Common PWM Features

CLKs

Data

Bus

Triggers

Interrupts

Each PWM Generator behaves as a separate peripheral that can be independently enabled from the other PWM

Generators. Each PWM Generator consists of a signal generator and an Output Control block.

The PWM Generators use ‘events’ to trigger other PWM Generators, ADC conversions and external operations. Each

PWM Generator accepts a trigger input and produces a trigger output. The trigger input signals the PWM Generator

when to start a new PWM period. The trigger output is generated when the trigger time value is equal to the PWM

Generator timer value.

Output Control blocks provide the capability to alter the base PWM signal sent to the output pins and incorporate

several functions, including:

• Output mode selection (Complementary, Push-Pull, Independent)

• Dead-time generator

• PWM Control Input (PCI) block

• Leading-Edge Blanking (LEB)

• Override

Each PWM Generator Output block is associated with the control of two PWM output pins. Output blocks contain a

PWM Control Input (PCI) that can be used for many purposes, including Fault detection, external triggering and

interfacing with other peripherals. The LEB block works in conjunction with the PCI block and allows PCI inputs to be

ignored during certain periods of the PWM cycle. The Override block determines the PWM output pin states during

various types of events, including Faults, current limit and feed-forward control. A block diagram of a single PWM

Generator is shown in .Figure 3-2

HRPWM with Fine Edge Placement

Architecture Overview

Figure 3-2. Single PWM Generator

Dead-Time

MPHASE[15:0]

PGxPHASE[15:0]

MDC[15:0]

PGxDC[15:0]

MPER[15:0]

PGxPER[15:0]

Master/Local

Data Register

Selection

MPHSEL

MDCSEL

MPERSEL

PGMOD[1:0]

CLK

TRIG

PWM

Generator

CLKSEL[1:0]

TRIGMOD[1:0]

PWM Generator

Sync/Trigger

Inputs

PCI Sync Active

SOCS[3:0]

External PWM

Control Inputs 1-31

PSS[4:0]

PCI Sync Logic

PCI Fault Logic

PCI Current

PCI Feed-Fwd

Logic

Limit Logic

PCI Fault Active

PCI Current Limit Active

PCI Feed-Forward Active

Blanking Active

Output

Override

Control and

Prioritization

Leading-Edge

Blanking Blanking Signals from

Other PGs

PWMxH

PWMxL

Combo

PWM

MUXing

POLH

POLL

HREN

High Res

Logic

Override

and

SWAP

Logic

Output

Control and

Dead-Time

Generator

Complementary

Mode Override

and SWAP

Logic

PMOD[1:0]

Dead-Time

Data Registers

Capture

Time Base

Capture

Trigger

Data Registers

Data

Update

Control

Frequency

Scaling

Clock

Divider

MCLKSEL[1:0]

Compensation

Data Register

raw_pwm

PWM Generator operation is based on triggers. To generate a PWM cycle, a SOC (Start-of-Cycle) trigger must be

received; the trigger can either be self-triggered or from an external source. illustrates a basic PWMFigure 3-3

waveform, showing SOC and EOC (End-of-Cycle) events. The PWMxH output starts the cycle ‘active’ (logic high),

and when the internal counter reaches the duty cycle value, it transitions to ‘inactive’ (logic low). EOC is reached

when the counter value reaches the period value.

Some operating modes and output modes use multiple counter cycles to produce a single PWM cycle. Refer to 4.2.2

PWM Modes 4.2.3 Output Modes and for more information.

HRPWM with Fine Edge Placement

Architecture Overview

Figure 3-3. Basic PWM Waveform

SOC

PWM

Timer

PWMx

0

Duty Cycle

EOC

Period

HRPWM with Fine Edge Placement

Architecture Overview

4. Operation

4.1 PWM Clocking

4.1.1 Master Clocking

The PWM module provides several clocking features at the top level of the module. Each PWM Generator can then

independently select one of the clock sources, as shown in . The clock input into the PWM module isFigure 4-1

selected with the MCLKSEL[1:0] control bits (PCLKCON[1:0]). The available clock inputs are device-dependent; refer

to the device data sheet for availability. The CLKSEL[1:0] control bits (PGxCONL[4:3]) are used to select the clock for

each PWM Generator instance; see for details. Frequency scaling and the clock4.2.1 PWM Generator Clocking

divider are discussed in . The CLKSELx bits need to be changed from the default selection to4.3.3 Shared Clocking

allow the PWM Generator to function.

Figure 4-1. PWM Generator Clocking

clk source 3

clk source 2

clk source 1

clk source 0

MCLKSEL<1:0>

(1)

Frequency

Scaling

Clock

Divider

DIVSEL<1:0>

PWM Generator 1 Clock Select

No Clock

CLKSEL<1:0>

Master Clock Select

PG1_clk

pwm_

master_clk

PWM Generator x Clock Select

No Clock

CLKSEL<1:0>

PGx_clk

Note:

1. Clock inputs are device-specific. Refer to the device data sheet for availability.

Note: Writing MCLKSEL[1:0] to a non-zero value will request and enable the chosen clock source, whether any

PWM Generators are enabled or not. This allows a PLL, for example, to be requested and warmed up before using it

as a PWM clock source. For the lowest device power consumption, the MCLKSEL[1:0] bits should be set to the

value, ‘ ’, if all PWM Generators have been disabled.00

Changing the MCLKSEL[1:0] or CLKSEL[1:0] bits while ON (PGxCONL[15]) = ) is not recommended.1

Note: The CPU and PWM typically run at different clock speeds depending on the application requirements. If PWM

clock speed is equal or slower than the CPU, writes to registers may have delayed behavior. For example, if

SWTERM is used to clear a Fault, the instruction may need to be stretched with a instruction to ensure theREPEAT

PWM can detect the edge within its clock cycle.

4.1.2 Clocking Equations in Standard Resolution

Some modes of operation utilize multiple period matches to complete one PWM ‘cycle’. The following equation

provides timing equations for the various operating modes.

HRPWM with Fine Edge Placement

Operation

Equation: PWM Period Calculation, Standard Resolution

Edge-Aligned, Variable Phase

Operating Modes

FPWM =

FPGx_clk

PGxPER + 1

Center-Aligned Modes,

Edge-Aligned and Variable Phase Modes

FPWM =

FPGx_clk

2 • (PGxPER + 1)

with Push-Pull Output Mode

Center-Aligned Modes

with Push-Pull Output Mode

PGxPER = FPGx_clk

FPWM



– 1

Where:

FPWM = Switching Frequency

PWM Period = 1/F PWM

PGxPER = FPGx_clk

2 • FPWM



– 1

FPWM =

FPGx_clk

4 • (PGxPER + 1)

PGxPER = FPGx_clk

4 • FPWM



– 1

Equation: PWM Duty Cycle, Phase, Trigger and Dead-Time Calculations, Standard Resolution

MDC or PGxDC(A) = (PGxPER + 1) • Duty Cycle

Where:

Duty Cycle is % between 0 and 100

MPHASE or PGxPHASE = F

PGx_clk • Phase

Where:

Phase, Trigger Offset and Dead Time are specified

in time units (ms, µs or ns)

PGxTRIGy = FPGx_clk • Trigger Offset

(y = A, B or C)

PGxDTy = FPGx_clk

• Dead Time

( )y = H or L

HRPWM with Fine Edge Placement

Operation

4.1.3 High-Resolution Mode

High-Resolution mode is not available on all devices. Refer to the device-specific data sheet for availability.

The PWM Generators may operate in High-Resolution mode to enhance phase, duty cycle and dead-time resolution

up to 250 ps. High-Resolution mode cannot be used with frequency scaling or the clock divider. To enable High-

Resolution mode for a given PWM Generator, set the HREN control bit (PGxCONL[7]). The HRRDY status bit

(PCLKCON[15]) indicates when the high-resolution circuitry is ready and the HRERR bit (PCLKCON[14]) indicates a

clocking error has occurred. When operating in high resolution, Dual PWM mode cannot be used in conjunction with

Complementary Output mode.

Note: When using High-Resolution mode, the CLKSEL[1:0] bits (PGxCONL[4:3]) must be set to ‘ ’ to select01

pwm_master_clk directly, and the pwm_master_clk must be configured for the correct frequency. Refer to the PWMx

Module Timing Requirements within the section of the device data sheet for this value.“Electrical Characteristics”

For dsPIC33C devices, the pwm_master_clk frequency must be 500 MHz in High-Resolution mode.

4.1.3.1 Data Registers in High Resolution

When High-Resolution mode is selected, some of the PWM Data registers have limited resolution. For some

registers, the Least Significant bits (LSbs) of the data value are forced to ‘ ’, regardless of the value written to the0

register. When configuring the PWM in High-Resolution mode, first set the HREN bit before writing data registers

whose function is dependent on High-Resolution mode. High-resolution operational differences are summarized in

Table 4-1.

Table 4-1. PWM Data Registers, High-Resolution Mode

Register Bits

15:3 2 1 0

PGxLEB 000

PGxPHASE

PGxDC

PGxDCA 000

PGxPER

PGxTRIGA(B)(C) (Notes 2, 5) 000

PGxDT (Note 1)

PGxCAP (Note 3)

FSCL (Note 4)

FSMINPER (Note 4)

MPHASE

MDC

MPER

Notes:

1. The DTH and DTL register sizes are retained in High-Resolution mode. See the and PGxDTL PGxDTH

registers for details.

2. Bit 15 of the PGxTRIGy registers selects the counter phase that produces the

trigger when operating in Center-Aligned modes.

3. Bits 1 and 0 will read as ‘ ’ in Standard Resolution mode. In High-Resolution mode, bits[4:0] will read as ‘ ’.0 0

4. Not used in High-Resolution mode.

5. In Dual PWM mode, the PGxTRIGA and PGxTRIGB registers will be used to set the rising and falling edge

of the 2nd PWM signal, and the three LSbs will be utilized.

HRPWM with Fine Edge Placement

Operation

4.1.3.2 Clocking Equations in High Resolution

Period calculations, when using High-Resolution mode, are shown in the following equations.

Equation: PWM Period Calculation, High-Resolution Mode

Edge-Aligned, Variable Phase

Operating Modes

FPWM =

8 • FPGx_clk

(PGxPER + 8)

Center-Aligned Modes,

Edge-Aligned and Variable Phase Modes

FPWM =

4 • FPGx_clk

(PGxPER + 8)

with Push-Pull Output Mode

Center-Aligned Modes

with Push-Pull Output Mode

FPWM =

2 • FPGx_clk

(PGxPER + 8)

PGxPER =

8 • FPGx_clk

FPWM







– 8

PGxPER =

4 • FPGx_clk

FPWM







– 8

PGxPER =2 • FPGx_clk

FPWM







– 8

Where:

FPWM = Switching Frequency

PWM Period = 1/FPWM

HRPWM with Fine Edge Placement

Operation

Equation: PWM Duty Cycle, Phase, Trigger and Dead-Time Calculations, High Resolution

MDC or PGxDC(A) = (PGxPER + 8) • Duty Cycle

MPHASE or PGxPHASE = 8 • FPGx_clk • Phase

PGxTRIGy = 8 • FPGx_clk • Trigger Offset

PGxDTy = 8 • FPGx_clk • Dead Time

(y = A, B or C)

( )y = H or L

Where:

Duty Cycle is % between 0 and 100

Where:

Phase, Trigger Offset and Dead Time are specified

in time units (ms, µs or ns)

4.1.3.3 High-Resolution Period Synchronization

When operating in High-Resolution mode, it is possible for PWM output edges to not be aligned with PGx_clk that the

rest of the PWM module operates at. When PGxPER (or MPER) values are not divisible by eight, the period contains

a fractional value of PGx_clk. This fractional clock difference can cause other events, including End-of-Cycle (EOC),

triggers, etc., to not align with the output edges. The module contains an accumulator circuit to calculate and

minimize the offset over long time periods.

If synchronous behavior is desired, it is recommended to use PGxPER values with bits[2:0] equal to ‘ ’.0

The fine edge placement circuit itself adds delay to the PWM outputs when compared to the base PWM signal. Using

the base PWM signal for gating and synchronization in High-Resolution mode may cause unexpected results for a

few fine edge clock cycles in some cases. For example, using the PCI’s auto-terminate feature will remove an

override condition at EOC and places the PWM outputs back to their existing state. Override is applied after the fine

edge placement circuit, as shown in Figure 4-11 Figure 4-15 and . Since the EOC event is based on the base PWM

signal, the delay through the fine edge circuit may be observed before the next PWM cycle is started. This behavior

can be mitigated by using a PHASE offset equal to PGxPER – 8.

In addition to EOC events, using timers operating on the base PWM signal (such as LEB and PGxTRIGy) or other

PWM Generators as a source may also be susceptible in some conditions.

4.1.4 Clocking Synchronization

Due to the separate clocking domains of the PWM module and the CPU’s system clock, there are inherent

synchronization delays associated with SFR reads. This delay is dependent on the relative speeds of the CPU

(sys_clk) and the PWM Generator clock (PGx_clk). Typically, the CPU clock will be slower and SFR data can be

delayed up to one sys_clk cycle. It is also important to note that each PWM Generator can run at a different speed

and this can have an effect on interactions between PWM Generators.

4.1.5 Minimum PWM Period and Pulse Width

The PWM module has some restrictions regarding minimum PWM periods and pulse widths. Depending on the

operating mode, the pulse width can also be dependent on PHASE and TRIGy, in addition to duty cycle. The

minimum pulse width applies to both active and inactive states; 0% and 100% duty cycles are supported.

Table 4-2 below lists restrictions to period and pulse width.

Table 4-2. Minimum Period and Pulse Width

Mode Minimum Period

(PGxPER or MPER)

Minimum Active Pulse

Width in Counts

Minimum Inactive Pulse

Width in Counts

Standard Resolution 0x0020 0x0008 Period – 0x0008

HRPWM with Fine Edge Placement

Operation

Marca:	Microchip
Categoría:	No categorizado
Modelo:	dsPIC33CK128MP505

Microchip dsPIC33CK128MP505 Manual de Usario

Especificaciones del producto

¿Necesitas ayuda?

No categorizado Microchip Manuales

No categorizado Manuales

Últimos No categorizado Manuales