Microchip DSPIC33EP256GM710 Manual de Usario

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High-Speed PWM

Section 14. High-Speed PWM

HIGHLIGHTS

This section of the manual contains the following major topics:

14.1 Introduction .................................................................................................................. 14-2

14.2 Features....................................................................................................................... 14-2

14.3 Control Registers ......................................................................................................... 14-3

14.4 Architecture Overview................................................................................................ 14-24

14.5 Module Description .................................................................................................... 14-27

14.6 PWM Operating Modes.............................................................................................. 14-33

14.7 PWM Generator......................................................................................................... 14-71

14.8 PWM Trigger.............................................................................................................. 14-87

14.9 PWM Interrupts.......................................................................................................... 14-98

14.10 PWM Fault Pins ......................................................................................................... 14-99

14.11 Special Features ...................................................................................................... 14-105

14.12 PWM Output Pin Control...........................................................................................14-111

14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113

14.14 Power-Saving Modes............................................................................................... 14-114

14.15 External Control of Individual Time Base(s)............................................................. 14-114

14.16 Application Information ............................................................................................ 14-115

14.17 Register Map............................................................................................................ 14-126

14.18 Related Application Notes........................................................................................ 14-127

14.19 Revision History ....................................................................................................... 14-128

dsPIC33E/PIC24E Family Reference Manual

14.1 INTRODUCTION

This section describes the High-Speed Pulse-Width Modulator (PWM) module and its

associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E

device family supports a wide variety of PWM modes and is ideal for power

conversion/motor control applications. Some of the common applications include:

• AC-to-DC converters

• DC-to-DC converters

• AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.

• Inverters

• Battery chargers

• Digital lighting

• Uninterrupted Power Supply (UPS)

• Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)

14.2 FEATURES

The High-Speed PWM module consists of the following major features:

• Up to seven PWM generators, each with an individual time base

• Two PWM outputs per PWM generator

• Individual period and duty cycle for each PWM output

• Duty cycle, dead time, phase shift and frequency resolution equal to the system clock

source (TOSC)

• Independent fault and current-limit inputs for up to 14 PWM outputs

• Redundant Output mode

• Independent Output mode (this feature is not available on all devices)

• Push-Pull Output mode

• Complementary Output mode

• Center-Aligned PWM mode

• Output override control

• Special Event Trigger

• PWM capture feature

• Prescaler for input clock

• ADC triggering with PWM

• Independent PWM frequency, duty cycle and phase shift changes

• Leading-Edge Blanking (LEB) functionality

• Dead time compensation

• Output clock chopping

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all dsPIC33E/PIC24E devices.

Please consult the note at the beginning of the “High-Speed PWM” chapter in the

current device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 14. High-Speed PWM

High-Speed PWM

14.3 CONTROL REGISTERS

The following registers control the operation of the High-Speed PWM module:

•PTCON: PWM Time Base Control Register

- Enables or disables the High-Speed PWM module

- Sets the Special Event Trigger for the ADC

- Enables or disables immediate period updates

- Selects the synchronizing source for the master time base

- Specifies synchronization settings

•PTCON2: PWM Clock Divider Select Register 2

Provides the clock prescaler to the PWM master time base

•PTPER: Primary Master Time Base Period Register

Provides the PWM time period value

•STCON: PWM Secondary Master Time Base Control Registe (1)

- Enables or disables immediate period updates based on the secondary master time base

- Selects the synchronization source for the secondary master time base

- Specifies the synchronization setting for secondary master time base control

• STCON2: PWM Secondary Clock Divider Select Register 2(1)

Provides the clock prescaler to the PWM secondary master time base

•STPER: Secondary Master Time Base Period Register(1)

Provides the secondary master time base period value

•MDC: PWM Master Duty Cycle Register

Provides the PWM master duty cycle value

•SEVTCMP: PWM Special Event Compare Register

Provides the compare value that is used to trigger the ADC module

•SSEVTCMP: PWM Secondary Special Event Compare Register(1)

Provides the compare value that is used to trigger the ADC module based on the

secondary master time base

•CHOP: PWM Chop Clock Generator Register

- Provides the chop clock frequency

- Enables or disables the chop clock generator

•PWMKEY: PWM Unlock Register(1)

Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers

•PWMCONx: PWM Control Register

- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt

- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger

interrupt

- Selects the type of time base (master time base or independent time base)

- Selects the type of duty cycle (master duty cycle or independent duty cycle)

- Controls Dead Time mode

- Enables or disables Center-Aligned mode

- Controls the external PWM Reset operation

- Enables or disables immediate updates of the duty cycle, phase offset, independent time

base period

•IOCONx: PWM I/O Control Register

- Enables or disables PWM pin control feature (PWM control or GPIO)

- Controls fault/current limit override values

- Enables PWMxH and PWMxL pin swapping

- Controls the PWMxH and PWMxL output polarity

- Controls the PWMxH and PWMxL output if any of the following modes is selected:

• Complementary mode

• Push-Pull mode

• True Independent mode

Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”

chapter in the specific device data sheet for availability.

Section 14. High-Speed PWM

High-Speed PWM

R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SYNCEN(1) SYNCSRC<2:0>(1) SEVTPS<3:0>(1)

bit 7 bit 0

Legend: HC = Cleared in Hardware HS = Set in Hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTEN: PWM Module Enable bit

1 = PWM module is enabled

0 = PWM module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode

0 = PWM time base runs in CPU Idle mode

bit 12 SESTAT: Special Event Interrupt Status bit

1 = Special Event Interrupt is pending

0 = Special Event Interrupt is not pending

bit 11 SEIEN: Special Event Interrupt Enable bit

1 = Special Event Interrupt is enabled

0 = Special Event Interrupt is disabled

bit 10 EIPU: Enable Immediate Period Updates bit(1)

1 = Active Period register is updated immediately

0 = Active Period register updates occur on PWM cycle boundaries

bit 9 SYNCPOL: Synchronize Input and Output Polarity bit

(1)

1 = SYNCIx/SYNCO polarity is inverted (active-low)

0 = SYNCIx/SYNCO is active-high

bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)

1 = SYNCO output is enabled

0 = SYNCO output is disabled

bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)

1 = External synchronization of primary time base is enabled

0 = External synchronization of primary time base is disabled

bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)

These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed

PWM” chapter in the specific device data sheet for availability.

bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits

(1)

1111 = 1:16 postscaler generates Special Event trigger at every 16th compare match event

•

0001 = 1:2 postscaler generates Special Event trigger at every second compare match event

0000 = 1:1 postscaler generates Special Event trigger at every compare match event

Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user

application must program the period register with a value that is slightly larger than the expected period of

the external synchronization input signal.

dsPIC33E/PIC24E Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)

111 = Reserved

110 = Divide by 64

101 = Divide by 32

100 = Divide by 16

011 = Divide by 8

010 = Divide by 4

001 = Divide by 2

000 = Divide by 1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PTPER<15:8>(1)

bit 15 bit 8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0

PTPER<7:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits(1)

Note 1: 1 LSb = 1 Tosc. For example, 7.14 ns for 70 MIPS operation.

dsPIC33E/PIC24E Family Reference Manual

(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEVTCMP<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEVTCMP<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 SSEVTCMP<15:0>: Secondary Special Event Compare Count Value bits

The optional SSEVTCMP register and the optional secondary master time base provide an additional

Special Event Trigger. The secondary special event trigger also has its own postscaler controlled by

the SEVTPS<3:0> bits in the STCON register.

Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific

device data sheet for availability.

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

CHPCLKEN — — — — — CHOPCLK<9:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHOPCLK<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CHPCLKEN: Enable Chop Clock Generator bit

1 = Chop clock generator is enabled

0 = Chop clock generator is disabled

bit 14-10 Unimplemented: Read as ‘0’

bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits

Chop Frequency = (FP/PLKDIV) / (CHOPCLK<9:0> + 1)

As an example, for devices running at 60 MIPS, a value of all zeros will yield a 60 MHz chop clock

(period = 16.7 ns) with the PWM clock prescaler configured for fastest clock. A value of ‘0000000001’

in the CHOPCLK<9:0> bits will yield a 30 MHz chop clock with the PWM clock prescaler configured

for fastest clock.

Note: The chop clock generator operates with the Primary PWM Clock Prescaler bits (PCLKDIV<2:0>) in the

PTCON2 register.

Section 14. High-Speed PWM

High-Speed PWM

bit 7-6 DTC<1:0>: Dead Time Control bits

11 = Dead Time Compensation mode enabled

10 = Dead time function is disabled

01 = Negative dead time actively applied for Complementary Output mode(6)

00 = Positive dead time actively applied for all output modes

bit 5 DTCP: Dead Time Compensation Polarity bit(5)

1 = If DTCMPx pin = 0, PWMxL is shortened, and PWMxH is lengthened

If DTCMPx pin = 1, PWMxH is shortened, and PWMxL is lengthened

0 = If DTCMPx pin = 0, PWMxH is shortened, and PWMxL is lengthened

If DTCMPx pin = 1, PWMxL is shortened, and PWMxH is lengthened

bit 4 Unimplemented: Read as ‘0’

bit 3 MTBS: Master Time Base Select bit

1 = PWM generator uses the secondary master time base for synchronization and the clock source

for the PWM generation logic (if secondary time base is available)

0 = PWM generator uses the primary master time base for synchronization and the clock source for

the PWM generation logic

bit 2 CAM: Center-Aligned Mode Enable bit(2,3)

1 = Center-Aligned mode is enabled

0 = Edge-Aligned mode is enabled

bit 1 External PWM Reset Control bitXPRES: (4)

1 = Current-limit source resets primary local time base for this PWM generator if it is in Independent

Time Base mode

0 = External pins do not affect PWM time base

bit 0 IUE: Immediate Update Enable bit(3)

1 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are

immediate

0 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are

synchronized to the PWM time base

Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.

2: The Independent Time Base mode (ITB = 1 0) must be enabled to use Center-Aligned mode. If ITB = , the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled (PTEN = 1).

4: To operate in External Period Reset mode, the ITB bit must be set to ‘ ’ and the CLMOD bit in the 1

FCLCONx register must be set to ‘0’.

5: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.

6: Negative dead time is only implemented for Edge-Aligned mode (CAM = 0).

dsPIC33E/PIC24E Family Reference Manual

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — LEB<11:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEB<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PWMCAP<15:8>(1,2)

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PWMCAP<7:0>(1,2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PWMCAP<15:0>: Captured PWM Time Base Value bits(1,2)

The value in this register represents the captured PWM time base value when a leading edge is

detected on the current-limit input.

Note 1: The capture feature is only available on the primary output (PWMxH).

2: The feature is only active after LEB processing on the current-limit input signal is complete.

Section 14. High-Speed PWM

High-Speed PWM

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — BLANKSEL<3:0>(1)

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHOPSEL<3:0>(1) CHOPHEN CHOPLEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 BLANKSEL<3:0>: PWM State Blank Source Select bits(1)

The selected state blank signal blocks the current-limit and/or fault input signals (if enabled via the

BCH and BCL bits in the LEBCONx register).

1111 = PWMxH selected as state blank source

•

0001 = PWMxH selected as state blank source

0000 = No state blanking

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHOPSEL<3:0>: PWM Chop Clock Source Select bits(1)

The selected signal will enable and disable (CHOP) the selected PWM outputs.

1111 = PWMxH selected as CHOP clock source

•

0001 = PWMxH selected as CHOP clock source

0000 = Chop clock generator selected as CHOP clock source

bit 1 CHOPHEN: PWMxH Output Chopping Enable bit

1 = PWMxH chopping function is enabled

0 = PWMxH chopping function is disabled

bit 0 CHOPLEN: PWMxL Output Chopping Enable bit

1 = PWMxL chopping function is enabled

0 = PWMxL chopping function is disabled

Note 1: These bit selections are device dependent. Refer to the “High-Speed PWM” chapter of the specific

device data sheet for availability.

Especificaciones del producto

Marca:	Microchip
Categoría:	No categorizado
Modelo:	DSPIC33EP256GM710

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