Texas Instruments CD74HC533E Manual de Usario

Texas Instruments No categorizado CD74HC533E

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Data sheet acquired from Harris Semiconductor

SCHS187C

Features

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buered Inputs

• Three-State Outputs

• Bus Line Driving Capacity

• Typical Propagation Delay = 13ns at V

CC = 5V,

CL = 15pF, TA = 25oC (Data to Output)

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤µ1 A at VOL, VOH

Description

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are

high-speed Octal Transparent Latches manufactured with

silicon gate CMOS technology. They possess the low power

consumption of standard CMOS integrated circuits, as well as

the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch

enable (LE) is high. When the latch enable (LE) goes low the

data is latched. The output enable (OE) controls the

three-state outputs. When the output enable (OE) is high the

outputs are in the high impedance state. The latch operation

is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the

’HC563 and CD74HCT563 but have different pinouts. The

’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;

the latter are non-inverting types.

Ordering Information

PART NUMBER

TEMP. RANGE

(oC) PACKAGE

CD54HC533F3A -55 to 125 20 Ld CERDIP

CD54HC563F3A -55 to 125 20 Ld CERDIP

CD54HCT533F3A -55 to 125 20 Ld CERDIP

CD74HC533E -55 to 125 20 Ld PDIP

CD74HC563E -55 to 125 20 Ld PDIP

CD74HC563M -55 to 125 20 Ld SOIC

CD74HCT533E -55 to 125 20 Ld PDIP

CD74HCT563E -55 to 125 20 Ld PDIP

CD74HCT563M -55 to 125 20 Ld SOIC

January 1998 - Revised July 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC533, CD54/74HCT533,

CD54/74HC563, CD74HCT563

High-Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

[ /Title

(CD74H

C533,

CD74H

CT533,

CD74H

C563,

CD74H

CT563)

/Subject

(High

Speed

Pinouts

CD54HC533, CD54HCT533

(CERDIP)

CD74HC533, CD74HCT533

(PDIP)

TOP VIEW

CD54HC563

(CERDIP)

CD74HC563, CD74HCT563

(PDIP, SOIC)

TOP VIEW

Functional Block Diagram

HC/HCT533

1OE

GND

VCC

LE 11

1OE

GND

VCC

O D

TRUTH TABLE

OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT

L H H L

L H L H

L L l H

L L h L

H X X Z

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to

the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.

CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V 20mA. . . . . . . . . . . . . . . . . . . . . .±

DC Output Diode Current, IOK

For VO < -0.5V or V

O > VCC + 0.5V 20mA . . . . . . . . . . . . . . . . . . . . ±

DC Drain Current, per Output, I

For -0.5V < VO < V

CC + 0.5V 35mA. . . . . . . . . . . . . . . . . . . . . . . . . . ±

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or V

O < VCC + 0.5V 25mA . . . . . . . . . . . . . . . . . . . . ±

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, T

A . . . . . . . . . . . . . . . . . . . . . . -55

oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1) θ

JA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input